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Investigation on Readback Attacks for Intellectual Property Theft

Art der Arbeit:

Masterthesis

Veröffentlichung:

25.07.2019

Studiengang:

Masterstudiengang Embedded Systems Design

Zusammenfassung der Arbeit:

This master thesis focuses on the lntellectual Property theft in the FPGA market. The hardware used was Xilinx's ZYNQ Ultrascale+ MPSoC (ZCU102) device to verify the possibility of Intellectual Property (IP) to be stolen. Several IP theft attacks and their effects are discussed for the evaluation of this work. Amongst which readback attack is of the interest. The main objective of this master's thesis is to perform the readback attacks on the most recent device available in the market. To evaluate the readback attack on IP, three key features provided by the FPGA vendor is developed and investigated. The first feature is the Dynamic Partially Reconfiguration. This capability that the modern SoC FPGAs possess is analyzed by developing a design with two Reconfigurable Partitions (RP), each RP having two Reconfigurable Modules (RM). The second feature is using secure Boot. The custom circuits within the programmable logic and processing system is protected from unauthorized access. Boot image partitions are divided into specified number of blocks and each block is encrypted and authenticated. The third feature is to retrieve the PL configuration data. The application programmable interface of the driver modules are utilized to capture the data to a file.

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